Adaptive Digital DC/DC Controller with Drivers and Current Sharing ( 33 Page)
September 8, 2009
Typical Application Circuit
The following application circuit represents a typical
implementation of the ZL6100. For PMBus operation, it is
recommended to tie the enable pin (EN) to SGND.
The ZL6100 is an innovative mixed-signal power conversion
and power management IC based on Zilker Labs patented
Digital-DC technology that provides an integrated, high
performance step-down converter for a wide variety of power
Today’s embedded power systems are typically designed for
optimal efficiency at maximum load, reducing the peak
thermal stress by limiting the total thermal dissipation inside
the system. Unfortunately, many of these systems are often
operated at load levels far below the peak where the power
system has been optimized, resulting in reduced efficiency.
While this may not cause thermal stress to occur, it does
contribute to higher electricity usage and results in higher
overall system operating costs.
Zilker Labs’ efficiency-adaptive ZL6100 DC/DC controller
helps mitigate this scenario by enabling the power converter
to automatically change their operating state to increase
efficiency and overall performance with little or no user
Its unique PWM loop utilizes an ideal mix of analog and
digital blocks to enable precise control of the entire power
conversion process with no software required, resulting in a
very flexible device that is also very easy to use. An
extensive set of power management functions are fully
integrated and can be configured using simple pin
connections. The user configuration can be saved in an
internal non-volatile memory (NVM). Additionally, all
functions can be configured and monitored via the SMBus
hardware interface using standard PMBus commands,
allowing ultimate flexibility.
Once enabled, the ZL6100 is immediately ready to regulate
power and perform power management tasks with no
programming required. Advanced configuration options and
real-time configuration changes are available via the
C/SMBus interface if desired and continuous monitoring of
multiple operating parameters is possible with minimal
interaction from a host controller. Integrated sub-regulation
circuitry enables single supply operation from any supply
between 3V and 14V with no secondary bias supplies needed.
The ZL6100 can be configured by simply connecting its pins
according to Tables
Additionally, a comprehensive set of online tools
and application notes are available to help simplify the
design process. An evaluation board is also available to help
the user become familiar with the device. This board can be
evaluated as a standalone platform using pin configuration
settings. A Windows™-based GUI is also provided to enable
full configuration and monitoring capability via the
C/SMBus interface using an available computer and the
included USB cable.
Please refer to www.intersil.com for access to the most
up-to-date documentation or call your local Intersil sales
office to order an evaluation kit.
3 x 10µF
POWER GOOD OUTPUT
2 x 47µF
1. Ferrite bead is optional for input noise suppression
2. The I
C/SMBus requires pull-up resistors. Please refer to the I
C/SMBus specifications for more details.
3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices
connected). The 10 k
default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to the
DDC Bus section for more details.
No t e s :
1. F e r r i te be ad i s opti o n a l f o r i n p u t no i s e s u p p r e s s i o n
2. T he I
C /S M B u s r e quir e s pull- up r es is tors . P lea s e r e fe r to t he I
C/S M B us s p ec if ic at ions fo r m or e details .
3. T he DDC b u s requ i r es a pul l- up r e s i s tor.
T h e r e s i s t a n c e wi l l v a r y ba s e d o n t h e c a pac i ti v e l o a d i n g o f the bus ( a n d o n th e nu m ber of dev i c es
c o nn ec te d) . T h e 10k
Ω def au lt v alue, as s u m ing a m ax im u m of 1 00pF pe r de v ic e , pr ov id es th e n ec es s ar y 1µ s pu ll- up r is e tim e . P lea s e r e fe r to
the DDC B u s s e c ti o n f o r m o r e i n fo rm a tio n.
FIGURE 2. 12V TO 1.8V/20A APPLICATION CIRCUIT (4.5V UVLO, 10ms SS DELAY, 5ms SS RAMP)
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