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ISL80103IR15Z-T Datasheet(PDF) 8 Page - Intersil Corporation

Part # ISL80103IR15Z-T
Description  High Performance 2A and 3A LDOs
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL80103IR15Z-T Datasheet(HTML) 8 Page - Intersil Corporation

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8
FN6660.0
September 30, 2009
Power-Good Operation
The PGOOD circuit monitors VOUT and signals a fault
condition when VOUT is below 84% of the nominal output
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than VIN. During
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider, R1 and R2, is used to
set the output voltage as shown in Equation 1. The
recommended value for R2 is 500Ω to 1kΩ. R1 is then
chosen according to Equation 2:
Power Dissipation
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 3:
The maximum allowed junction temperature, TJ(MAX)
and the maximum expected ambient temperature,
TA(MAX) will determine the maximum allowed junction
temperature rise (ΔTJ) as shown in Equation 4:
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
resistance (θJA) for the DFN package with Equation 5:
Substitute PD for PD(MAX) and the maximum ambient
operating temperature can be found by solving for TA
using Equation 6:
Heatsinking The DFN Package
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 4
shows a curve for the θJA of the DFN package for
different copper area sizes.
V
OUT
0.5V
R
1
R
2
-------
1
+
⎝⎠
⎜⎟
⎛⎞
×
=
(EQ. 1)
R
1
R
2
V
OUT
0.5V
----------------
1
⎝⎠
⎛⎞
×
=
(EQ. 2)
P
D
V
IN
V
OUT
() I
OUT
V
IN
I
GND
×
+
×
=
(EQ. 3)
ΔT
J
T
JMAX
() TAMAX
()
=
(EQ. 4)
P
DMAX
()
T
JMAX
() TA
() θ
JA
=
(EQ. 5)
T
A
T
JMAX
P
DMAX
() θJA
×
=
(EQ. 6)
FIGURE 4. 3mmx3mm-10 Pin DFN ON 4-LAYER PCB
WITH THERMAL VIAS θJA vs EPAD-MOUNT
COPPER LAND AREA ON PCB
46
44
42
40
38
36
34
2468
10
12
14
16
18
20
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
2
ISL80102, ISL80103


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