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HI-3598 Datasheet(PDF) 8 Page - Holt Integrated Circuits |
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HI-3598 Datasheet(HTML) 8 Page - Holt Integrated Circuits |
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8 / 18 page  HI-3596, HI-3597, HI-3598, HI-3599 HOLT INTEGRATED CIRCUITS 8 3. To validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. With exactly 1MHz input clock frequency, the acceptable data bit rates are shown in Table 8. Table 8. Acceptable Data Bit Rates at 1MHz Input Clock Frequency HIGH SPEED LOW SPEED Data Bit Rate Min 83Kbps 10.4Kbps Data Bit Rate Max 125Kbps 15.6Kbps 4. Following the last data bit of a valid reception, the Word Gap timer samples the Null shift register every 10 input clocks (every 80 clocks for low speed). If a Null is present, the Word Gap counter is incre- mented. A Word Gap count of 3 enables the next reception. Receiver Parity If enabled by setting Control Register CR4 bit to “1”, the receiver parity circuit counts Ones received, including the parity bit. If the result is odd, then a “0” appears in the 32nd bit. Setting Control Register CR4 bit to “0” disables parity checking and all 32 bits are treated as data. Retrieving Data Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending on the state of Control Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC word is then checked for correct decoding and label match before it is loaded into the 4 x 32 Receive FIFO. ARINC words that do not match required 9th and 10th ARINC bit and do not have a label match are ignored and are not loaded into the Receive FIFO. Table 9 describes this operation. Table 9. FIFO Loading Control CR2 ARINC word matches Enabled label CR6 ARINC word bits 10, 9 match CR7, 8 FIFO 0 X 0 X Load FIFO 1 No 0 X Ignore Data 1 Yes 0 X Load FIFO 0 X 1 No Ignore Data 0 X 1 Yes Load FIFO 1 Yes 1 No Ignore Data 1 No 1 Yes Ignore Data 1 No 1 No Ignore Data 1 Yes 1 Yes Load FIFO Once a valid ARINC word is loaded into the FIFO, the EOS signal clocks the Data Ready flip-flop to a “1”, and the corresponding channel’s Status Register FIFO Empty bit (SR0- SR7) goes to a “0”. The channel’s Empty bit remains low until the corresponding Receive FIFO is empty. Each received ARINC word is retrieved via the SPI interface using SPI instruction n3 hex where “n” is the channel number 1-8 hex. Up to 4 ARINC words may be held in each channel’s Receive FIFO. The Status Register FIFO Full bit (SR8 - SR15) goes high when the corresponding channel’s Receive FIFO is full. Failure to offload a full Receive FIFO causes additional received valid ARINC words to overwrite the last received word. Label Recognition The user loads the 16 byte label look-up table to spec- ify which 8-bit incoming ARINC labels are captured by the receiver, and which are discarded. If fewer than 16 labels are required, spare label memory locations must be filled with duplicate copies of any valid label. After the look-up table is initialized, set channel Control Register bit CR2 to enable label recognition for that channel. If label recognition is enabled, the receiver compares the label in each new ARINC word against the channel’s stored label look-up table. If a label match is found, the received word is processed. If no match occurs, the new ARINC word is discarded and no indicators of received ARINC data are presented. Note that 00 hex is treated in the same way as any other label value. Label memory bit significance is not changed by the status of Control Register bit CR9. The most significant label bit is always |
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