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HI-3588PCT Datasheet(PDF) 5 Page - Holt Integrated Circuits

Part # HI-3588PCT
Description  ARINC 429 Receiver with SPI Interface
Download  11 Pages
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Manufacturer  HOLTIC [Holt Integrated Circuits]
Direct Link  http://www.holtic.com
Logo HOLTIC - Holt Integrated Circuits

HI-3588PCT Datasheet(HTML) 5 Page - Holt Integrated Circuits

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ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or Ze-
ros sampling shift register, and at least three consecutive Null
samples (three high bits) in the lower half of the Null sampling
shift register within the data bit interval.
A word gap Null requires at least three consecutive Null sam-
ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg-
ister. This guarantees the minimum pulse width.
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
83K BPS
10.4K BPS
125K BPS
15.6K BPS
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of 3
enables the next reception.
The receiver parity circuit counts Ones received, including the parity
bit. If the result is odd, a "0" appears in the 32nd bit.
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS).
Depending on the state of Control
Register bits CR2, and CR6 through CR8, the received 32-bit
ARINC word is then checked for correct decoding and label match
before it is loaded into the 32 x 32 Receive FIFO. ARINC words that
do not match required 9th and 10th ARINC bit and do not have a
label match are ignored and are not loaded into the Receive FIFO.
The table below describes this operation.
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED
LOW SPEED
RECEIVER PARITY
RETRIEVING DATA
FUNCTIONAL DESCRIPTION (cont.)
HI-3588
The HI-3588 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level). Design tolerances
guarantee detection of the above levels, so the actual acceptance
ranges are slightly larger. If the ARINC signal (including nulls) is
outside the differential voltage ranges, the HI-3588 receiver rejects
the data.
Figure 2 is a block diagram showing receiver logic.
The ARINC 429 specification defines the following timing toler-
ances for received data:
100K BPS ± 1%
12K -14.5K BPS
1.5 ± 0.5 µsec
10 ± 5 µsec
1.5 ± 0.5 µsec
10 ± 5 µsec
5 µsec ± 5%
34.5 to 41.7 µsec
The HI-3588 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 0.1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift reg-
isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-
RECEIVER LOGIC OPERATION
BIT TIMING
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
HIGH SPEED
LOW SPEED
0
X
0
X
Load FIFO
1
No
0
X
Ignore data
1
Yes
0
X
Load FIFO
0
X
1
No
Ignore data
0
X
1
Yes
Load FIFO
1
Yes
1
No
Ignore data
1
No
1
Yes
Ignore data
1
No
1
No
Ignore data
1
Yes
1
Yes
Load FIFO
CR2
ARINC word
CR6
ARINC word
FIFO
matches
bits 10, 9
Enabled
match
CR7,8
label
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the ARINC 429 line receiver. The
ARINC 429 specification requires the following detection levels:
ONE
+6.5 Volts to +13 Volts
NULL
+2.5 Volts to -2.5 Volts
ZERO
-6.5 Volts to -13 Volts
STATE
DIFFERENTIAL VOLTAGE
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
FIGURE 1. ARINC RECEIVER INPUT
RINA-40
RINA
RINB
RINB-40
VDD
GND
VDD
GND
ONE
NULL
ZERO
HOLT INTEGRATED CIRCUITS
5


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