FUNCTIONAL DESCRIPTION (cont.)

HI-3587

TRANSMITTER

FIFO OPERATION

The Transmit FIFO is loaded with ARINC 429 words awaiting

transmission. SPI op code 0E hex writes up to 32 ARINC words into

the FIFO, starting at the next available FIFO location.

If Status

Register bit SR3 equals “1” (FIFO empty), then up to 32 words

(32 bits each) may be loaded.

If Status Register bit SR3 equals “0”

then only the available positions may be loaded. If all 32 positions

are full, Status Register bit SR5 is asserted. Further attempts to load

the Transmit FIFO are ignored until at least one ARINC word is

transmitted.

The Transmit FIFO half-full flag (Status Register bit SR4) equals “0”

when the Transmit FIFO contains less than 16 words. When SR4

equals “0”, the system microprocessor can safely initiate a 16-word

ARINC block-write sequence.

In normal operation (Control Register bit CR3 = ”1”), the 32nd bit

transmitted is a word parity bit. Odd or even parity is selected by

programming Control Register bit CR9 to a “0” or “1” respectively. If

Control Register bit CR3 equals “0”, all 32 bits loaded into the

Transmit FIFO are treated as data and are transmitted.

SPI op code 11 hex asynchronously clears all data in the Transmit

FIFO.

If Control Register bit CR13 equals “1”, ARINC 429 data is

transmitted immediately following the

rising edge of the SPI

instruction that loaded data into the Transmit FIFO. Loading

Control Register bit CR13 to “0” allows the software to control

transmission timing; each time a 12 hex SPI op code is executed,

all loaded Transmit FIFO words are transmitted. If new words are

loaded into the Transmit FIFO before transmission stops, the new

words will also be output. Once the Transmit FIFO is empty and

transmission of the last word is complete, the FIFO can be loaded

with new data which is held until the next SPI 12 hex instruction is

executed. Once transmission is enabled, the FIFO positions are

incremented with the top register loading into the data transmission

shift register. Within 2.5 data clocks the first data bit appears at

AOUT and BOUT. The 31 or 32 bits in the data transmission shift

register are presented sequentially to the outputs in the ARINC 429

format with the following timing:

DATA TRANSMISSION

CS

FIGURE 1.

TRANSMITTER BLOCK DIAGRAM

DATA

CLOCK

CR10, CR1

PARITY

GENERATOR

DATA AND

NULL TIMER

SEQUENCER

LINE DRIVER

BIT

AND

WORD GAP

COUNTER

START

SEQUENCE

WORD COUNTER

AND

FIFO CONTROL

INCREMENT

WORD COUNT

DATA CLOCK

DIVIDER

FIFO

LOADING

SEQUENCER

AOUT

BOUT

32 x 32 FIFO

32 BIT PARALLEL

LOAD SHIFT REGISTER

BIT CLOCK

WORD CLOCK

ADDRESS

LOAD

SR3

SR4

SR5

SPI INTERFACE

SCK

CS

SI

SO

SPI COMMANDS

SPI COMMANDS

CR3, CR9

ACLK

CR12

ARINC 429 DATA FORMAT

Control Register bit CR11 controls how individual bits in the

transmitted ARINC word are mapped to the HI-3587 SPI data word

bits during data read or write operations.

The following table

describes this mapping:

Table 2. SPI / ARINC bit-mapping

SPI

1

2 - 22

23242526272829303132

Order

. ARINC bit 32

31 - 11

10

912345678

CR11=0

Data

ARINC bit 32

31 - 11

10

987654321

CR11=1

Data

HOLT INTEGRATED CIRCUITS

5