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HI-3585PCT Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-3585PCT Datasheet(HTML) 4 Page - Holt Integrated Circuits |
4 / 14 page CONTROL WORD REGISTER The HI-3585 contains a 16-bit Control Register which is used to configure the device. Control Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction 10 hex. The Control Register contents may be read using SPI instruction 0B hex. Each bit of the Control Register has the following function: STATUS REGISTER The HI-3585 contains an 8-bit Status Register which can be interrogated to determine the status of the ARINC receiver, data FIFOs and transmitter. The contents of the Status Register are output using SPI instruction 0A hex. Unused bits are output as Zeros. The following table defines the Status Register bits. SR Bit FUNCTION STATE DESCRIPTION SR0 Receive FIFO 0 1 Receiver FIFO is empty Receiver FIFO contains valid data (LSB) Empty Sets to One when all data has been read. RFLAG pin reflects the state of this bit when CR15=0 SR1 Receive FIFO 0 Receiver FIFO holds less than 16 Half Full words 1 Receiver FIFO holds at least 16 words SR2 Receive FIFO 0 Receiver FIFO not full. RFLAG pin Full reflects the state of this bit when CR15=1 1 Receiver FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period SR3 Transmit FIFO 0 Transmit FIFO not empty. Empty Sets to One when all data has been sent. TFLAG pin reflects the state of this bit when CR14=0 1 Transmit FIFO is empty. SR4 Transmit FIFO 0 Transmit FIFO contains less than 16 Half Full words 1 Transmit FIFO contains at least 16 words SR5 Transmit FIFO 0 Transmit FIFO not full. TFLAG pin Full reflects the state of this bit when CR14=1 1 Transmit FIFO full. SR6 Not used 0 Always “0” SR7 Not used 0 Always “0” (MSB) CR Bit FUNCTION STATE DESCRIPTION Cr0 Receiver 0 Data rate = CLK/10 1 Data rate = CLK/80 (ARINC 429 High-Speed) (LSB) Data Rate Select (ARINC 429 Low-Speed) CR1 ARINC Clock 0 ARINC CLK = ACLK input frequency Source Select 1 ARINC CLK = ACLK divided by the value programmed with SPI Instruction 07 hex CR2 Enable Label 0 Label recognition disabled Recognition 1 Label recognition enabled CR3 Transmitter 0 Transmitter 32nd bit is data Parity Bit Enable 1 Transmitter 32nd bit is parity CR4 Receiver 0 Receiver parity check disabled Parity Check Enable 1 Receiver odd parity check enabled CR5 Self Test 0 The transmitter’s digital outputs are internally connected to the receiver logic inputs 1 Normal operation CR6 Receiver 0 Receiver decoder disabled Decoder 1 ARINC bits 10 and 9 must match CR7 and CR8 CR7 - - If receiver decoder is enabled, the ARINC bit 10 must match this bit CR8 - - If receiver decoder is enabled, the ARINC bit 9 must match this bit CR9 Transmitter 0 Transmitter 32nd bit is Odd parity Parity Select 1 Transmitter 32nd bit is Even parity CR10 Transmitter 0 Data rate = CLK/10, O/P slope = 1.5us Data Rate 1 Data rate = CLK/80, O/P slope = 10us CR11 ARINC Label 0 Label bit order reversed (See Table 2) Bit Order 1 Label bit order same as transmitted / received (See Table 2) CR12 Disable 0 Line Driver enabled Line Driver 1 Line Driver disabled (force outputs to Null state) CR13 Transmission 0 Start transmission by SPI Enable Mode instruction12 hex 1 Transmit whenever data is available in the Transmit FIFO CR14 TFLAG 0 TFLAG goes high when transmit FIFO is empty Definition 1 TFLAG goes high when transmit FIFO is full CR15 RFLAG 0 RFLAG goes high when receive FIFO is empty (MSB) Definition 1 RFLAG goes high when receive FIFO is full FUNCTIONAL DESCRIPTION HI-3585 HOLT INTEGRATED CIRCUITS 4 |
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