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HI-6121PCIF Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-6121PCIF Datasheet(HTML) 4 Page - Holt Integrated Circuits |
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4 / 116 page  ESCK OUTPUT Serial Clock output signal for the dedicated auto-initialization SPI connected to external auto-initialization EEPROM. MISO INPUT Serial Input signal (Master-In Slave-Out) for the dedicated auto-initialization SPI connected to external auto-initialization EEPROM. MOSI OUTPUT Serial Output signal (Master-Out Slave-In) for the dedicated auto-initialization SPI connected to external auto-initialization EEPROM. TEST INPUT Test enable. The host asserts this pin to perform RAM self-test or loopback tests. TEST7:0 BI-DIR Test pins used for factory testing. Do not connect these pins. MODE INPUT Test pin used for factory testing. Do not connect this pin. COMP INPUT Test pin used for factory testing. Do not connect this pin. INPUT B ACKHW* INPUT Hardware Interrupt Acknowledge, active high. only used when the INTSEL bit in Configuration Register 1 is asserted to enable level interrupts. After interrupt assertion causes the output to go low, a high state (60ns minimum duration) on ACKHW will clear the output to logic 1. The interrupt is also cleared by reading the Pending Interrupt Register. ACKMES* INPUT Message Interrupt Acknowledge, active high. only used when the INTSEL bit in Configuration Register 1 is asserted to enable level interrupts. After interrupt assertion causes the output to go low, a high state (60ns minimum duration) on ACKMES will clear the output to logic 1. The interrupt is also cleared by reading the Pending Interrupt Register. CE INTHW INTHW INTMES INTMES Internal 50K pull-down resistor. Internal 50K pull-down resistor. Internal 50K pull-down resistor. Internal 50K pull-up resistor. Internal 50K pull-down resistor. Chip Enable, active low. Internal 50K pull-up resistor. When asserted, this pin enables host read or write accesses to device RAM or registers. On HI-6121, it is normally connected to a host SPI chip select output signal. ENDI INPUT Configuration pin for selecting “endianness” of the host bus interface when byte transfers are used. Internal 50K pull-up resistor. Endianness is the system attribute that indicates whether integers are represented with the most significant byte stored at the lowest address (big endian) or at the highest address (little endian). Internal storage is “big endian.” When using the HI-6120, this pin only applies when the host bus is configured for 8-bit width, that is, when BWID equals 0. When the HI-6120 is configured for 16-bit bus width, the BENDI input pin is “don’t care.” When using the HI-6121, this pin controls the byte order of the 16-bit data following the SPI command. When BENDI is low, “little endian” is chosen; the low order byte (bits 7:0) is transacted before the high order byte (bits 15:8). When BENDI is high, “big endian” is chosen and the high order byte is transacted on the host bus before the low order byte. Internal 50K pull-down resistor. This input is Internal 50K pull-down resistor. This input is W W W W W W W W W BUSA, ANALOG Bi-directional analog interface to MIL-STD-1553 bus A isolation transformer, positive and negative signals respectively. BUSB, ANALOG Bi-directional analog interface to MIL-STD-1553 bus B isolation transformer, positive and negative signals respectively. VCC, VCCP POWER 3.3V supply voltage inputs for logic and transceiver circuits GND POWER Ground pin for logic and transceiver circuits BUSA BUSB THESE PINS APPLY TO BOTH HI-6120 AND HI-6121 PIN DESCRIPTION, Cont. PIN TYPE DESCRIPTION * Note: These pins are combined into the ACKINT pin on HI-6121PQx variant. HOLT INTEGRATED CIRCUITS 4 HI-6120, HI-6121 |
Similar Part No. - HI-6121PCIF |
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Similar Description - HI-6121PCIF |
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