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HI-6120PQIF Datasheet(PDF) 9 Page - Holt Integrated Circuits |
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HI-6120PQIF Datasheet(HTML) 9 Page - Holt Integrated Circuits |
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9 / 116 page  REGISTERS Residing at the start of the memory address space, 32 addresses are reserved for HI-6120 and HI-6121 registers. Register addresses overlay the shared RAM address space, but are separate from the shared dual-port RAM. All register bits are active high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset (except any bits reflecting the state of input pins). For all registers, bit 15 is the most significant: 0 0x0000 Configuration Register 1 1 0x0001 Configuration Register 2 2 0x0002 Operational Status Register 3 0x0003 Current Command Register 4 0x0006 Pending Interrupt Register 7 0x0007 1553 Status Word Bits Register 8 0x0008 Time-Tag Register 9 0x0009 Interrupt Log Address Register 10 0x000A Current Message Information Word Address Register -31 0x001A-0x001F Reserved (0x0000) This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high. 15 INHBUSA Bus A Inhibit. When set, this bit disables transmit and receive for Bus A. This bit is logically ORed with the TXINHA input signal to control Bus A transmitter enablement. Bus A transmission is disabled if the INHBUSA register bit or TXINHA input pin is asserted. The TXINHA pin does not affect the Bus A receiver. 14 INHBUSB Bus B Inhibit. Register Hex Number Address Register Name Bit No. Mnemonic Function CONFIGURATION REGISTER 1 0x0004 Current Control Word Address Register 5 0x0005 Descriptor Table Base Address Register 6 11-14 0x000B-0x000E Reserved 15 0x000F Memory Address Pointer (HI-6121 Only) 16 0x0010 Interrupt Enable Register 17 0x0011 Time-Tag Utility Register 18 0x0012 Bus A Select Register 19 0x0013 Bus B Select Register 20 0x0014 Built-In Test (BIT) Word Register 21 0x0015 Alternate Built-In Test (BIT) Word Register 22 0x0016 Reserved 23 0x0017 Test Control Register 24 0x0018 Loopback Test Transmit Data Register 25 0x0019 Loopback Test Receive Data Register 26 This register is cleared after pin Master Reset. After SRST software reset, the SRST bit is reset; the remaining bits are unchanged. When set, this bit disables transmit and receive for Bus B. This bit is logically ORed with the TXINHB input signal to control Bus B transmitter enablement. Bus B transmission is disabled if the INHBUSB register bit or TXINHB input pin is asserted. The TXINHB pin does not affect the Bus B receiver. 13 INTSEL Interrupt Mode Select. When this bit is low, pulse interrupt outputs are selected for and output pins. When this bit is high, level interrupts are enabled which require host acknowledgment for interrupt pin reset. MR INTMES INTHW MSB LSB 15 14 13 12 11 10 9876543210 X X HOLT INTEGRATED CIRCUITS 9 HI-6120, HI-6121 |
Similar Part No. - HI-6120PQIF |
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Similar Description - HI-6120PQIF |
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