HSD128M72B9K-F12 datasheet(6/11 Pages) HANBIT

Part #	HSD128M72B9K-F12

Description	Synchronous DRAM Module 1024Mbyte (128Mx72Bit), 8K Ref., 3.3V ECC Unbuffered SO-DIMM,

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Manufacturer	HANBIT [Hanbit Electronics Co.,Ltd]

Direct Link	http://www.hbe.co.kr

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HANBit

HSD128M72B9K

URL : www.hbe.co.kr

HANBit Electronics Co.,Ltd.

REV.0.0(January. 2003)

6

ICC2NS

CKE

³ VIH(min)

CLK

£ VIL(max), tCC=¥

Input signals are stable

180

ICC3P

CKE

£ VIL(max), tCC=10ns

72

Active

standby

current

in

power-down mode

ICC3PS

CKE&CLK

£ VIL(max)

tCC=¥

72

mA

ICC3N

CKE

³VIH(min),

CS*

³VIH(min), tCC=10ns

Input signals are changed one

time during 20ns

450

Active standby current in

non power-down mode

(One bank active)

ICC3NS

CKE

³VIH(min)

CLK

£VIL(max), tCC=¥

Input signals are stable

315

mA

Operating current

(Burst mode)

ICC4

IO = 0 mA

Page burst

4Banks Activated

tCCD = 2CLKs

1260 1260 1170 1170

mA

1

Refresh current

ICC5

tRC ³ tRC(min)

2160 1980 1890 1890

mA

2

54

mA

3

Self refresh current

ICC6

CKE

£ 0.2V

27

mA

4

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

AC OPERATING TEST CONDITIONS

(Vcc = 3.3V ± 0.3V, TA = 0 to 70° C)

PARAMETER

Value

UNIT

AC Input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

+3.3V

Vtt=1.4V

50

W

50pF

DOUT

Z0=50

W

1200

W

870

W

50pF*

DOUT

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

(Fig. 1) DC output load

(Fig. 2) AC output load circuit

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