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ATxmega16A4-MH Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATxmega16A4-MH Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 104 page  8 8069L–AVR–11/09 XMEGA A4 6. AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack Pointer accessible in I/O memory space • Direct addressing of up to 16M Bytes of program and data memory • True 16/24-bit access to 16/24-bit I/O registers • Support for 8-, 16- and 32-bit Arithmetic • Configuration Change Protection of system critical features 6.2 Overview The XMEGA A4 uses the 8/16-bit AVR CPU. The main function of the CPU is program execu- tion. The CPU must therefore be able to access memories, perform calculations and control peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 8 shows the CPU block diagram. Figure 6-1. CPU block diagram The AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This Flash Program Memory Instruction Decode Program Counter OCD 32 x 8 General Purpose Registers ALU Multiplier/ DES Instruction Register STATUS/ CONTROL Peripheral Module 1 Peripheral Module 2 EEPROM PMIC SRAM DATA BUS DATA BUS |
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