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R5F35L26DFE Datasheet(PDF) 8 Page - Renesas Technology Corp |
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R5F35L26DFE Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 85 page REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 8 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 1.4 Block Diagram Figure 1.3 shows a block diagram of M16C/5LD Group, M16C/56D Group 80-pin package. Figure 1.4 shows a block diagram of the M16C/5LD Group, M16C/56D Group 64-pin package. Figure 1.3 M16C/5LD Group, M16C/56D Group 80-Pin Block Diagram Port P0 Port P1 Port P2 Port P3 8 8 8 8 Peripherals Timer (16-bit) Output (timer A): 5 Input (timer B): 3 Three-phase motor control circuit Timer S (Input capture/output compare) Time measurement: 8 channels Waveform generating: 8 channels A/D converter (10-bit x 27 channels) (A/D circuit) (10-bit x 4 channels) (A/D1 circuit) UART/clock synchronous serial interface (8-bit x 5 channels) Multi-master I2C bus Clock generator XIN-XOUT XCIN-XCOUT 125-kHz on-chip oscillator PLL frequency synthesizer CAN module (32-slot message buffer, 1 channel) (M16C/5LD Group only) W atchdog timer (15 bits) CRC calculator (CCITT, CRC-16) DMAC (4 channels) M16C/60 Series CPU core R3 FB SB INTB USP ISP PC FLG R0H R0L R1H R1L R2 R3 A0 A1 FB Memory ROM (1) RAM (2) Multiplier Notes: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type I/O ports Task monitoring timer (1 channel) Real-time clock (8-bit x 1 channel) 125-kHz on-chip oscillator dedicated to watchdog timer Power-on reset Voltage detector On-chip debugger |
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