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AT7913EKB-SV Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT7913EKB-SV Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 18 page  6 AT7913E Advanced Information 7833B–AERO–05/09 ADWr O DAC write strobe ADCs O ADC chip select ADRc O ADC read/convert ADRdy I ADC ready ADTrig I ADC trigger MemA[22:0] O Memory interface address - These active high outputs carry the address during accesses on the memory bus. When no access is performed, the address of the last access is driven (also internal cycles). MemD[31:0] IO Memory interface data - MemD[31:0] carries the data during transfers on the memory bus. The processor only drives the bus during write cycles. During accesses to 8-bit areas, only MemD[31:24] are used. MemCB[7:0] IO Memory interface checkbitsMemCB[6:0] carries the EDAC checkbits, MemCB[7] takes the value of TB[7] in the error control register. The processor only drive MemCB[7:0] during write cycles to areas programmed to be EDAC protected MemCsN[3:0] O SRAM chip select - These active low signals provide an individual output enable for each SRAM bank. MemOeN[3:0] O SRAM output enable -These active low outputs provide the chip-select signals for each SRAM bank. MemWrN[3:0] O SRAM byte write strobe - These active low outputs provide individual write strobes for each byte lane. MemWrN[0] controls MemD[31:24], MemWrN[1] controls MemD[23:16], etc. RomCsN[1:0] O PROM chip select - These active low outputs provide the chip- select signal for the PROM area. RomCsN[0] is asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while RomCsN[1] is asserted for the upper half. IoCsN O I/O area chip select - This active low output is the chip-select signal for the memory mapped I/O area. IoOeN O I/O area output enable - This active low output is asserted during read cycles on the memory bus. IoRead O I/O area read - This active high output is asserted during read cycles on the memory bus. IoWrN O I/O area write - This active low output provides a write strobe during write cycles on the memory bus. IoBrdyN I I/O area ready - This active low input indicates that the access to a memory mapped I/O area can be terminated on the next rising clock edge. |
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