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HMD32M32M16EG Datasheet(PDF) 6 Page - Hanbit Electronics Co.,Ltd

Part # HMD32M32M16EG
Description  128Mbyte (32Mx32) 72-pin EDO Mode 4K Ref. SIMM Design 5V
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Manufacturer  HANBIT [Hanbit Electronics Co.,Ltd]
Direct Link  http://www.hbe.co.kr
Logo HANBIT - Hanbit Electronics Co.,Ltd

HMD32M32M16EG Datasheet(HTML) 6 Page - Hanbit Electronics Co.,Ltd

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HANBiT
HMD32M32M16EG
URL:www.hbe.co.kr
HANBiT Electronics Co.,Ltd.
REV.1.0 (August. 2002)
- 6 -
AC CHARACTERISTICS ( 0
o
C
≤ T
A ≤ 70
oC , Vcc = 5V±10%)
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNIT
NOTE
Hyper page mode cycle time
tHPC
20
25
ns
11
/CAS precharge time (Hyper page cycle)
tCP
8
10
ns
/RAS pulse width (Hyper page cycle)
tRASP
50
200K
60
200K
ns
/RAS hold time from /CAS precharge
tRHCP
30
35
ns
/W to RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to RAS hold time (C-B-R refresh)
tWRH
10
10
ns
Output data hold time
tDOH
5
5
ns
Output buffer turn off delay from /RAS
tREZ
3
13
3
15
ns
6,12
Output buffer turn off delay from W
tWEZ
3
13
3
15
ns
6
/W to data delay
tWED
15
15
ns
/W puls width
tWPE
5
5
ns
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh
cycles before proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference
point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD ≥ tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit and is not referenced for VOH or VOL.
7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If
tWCS ≥ tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration
of the cycle.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the /CAS leading edge in early write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point
only. If tRAD is greater than the specified tRAD(max) limit access time is controlled by tAA.
11. tASC
≥6ns, Assume t T=2.0ns.
12. If /RAS goes high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going.
If /CAS goes high before /RAS high going , the open circuit condition of the output is achieved by /RAS going.
.


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