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AT91SAM7XC512 Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT91SAM7XC512 Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 727 page  8 6209F–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary Note: 1. Refer to Section 6. ”I/O Lines Considerations”. Analog-to-Digital Converter AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset. AD4-AD7 Analog Inputs Analog Analog Inputs ADTRG ADC Trigger Input ADVREF ADC Reference Analog Fast Flash Programming Interface PGMEN0-PGMEN1 Programming Enabling Input PGMM0-PGMM3 Programming Mode Input PGMD0-PGMD15 Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input Low CAN Controller CANRX CAN Input Input CANTX CAN Output Output Ethernet MAC 10/100 EREFCK Reference Clock Input RMII only ETXCK Transmit Clock Input MII only ERXCK Receive Clock Input MII only ETXEN Transmit Enable Output ETX0 - ETX3 Transmit Data Output ETX0 - ETX1 only in RMII ETXER Transmit Coding Error Output MII only ERXDV Receive Data Valid Input MII only ECRSDV Carrier Sense and Data Valid Input RMII only ERX0 - ERX3 Receive Data Input ERX0 - ERX1 only in RMII ERXER Receive Error Input ECRS Carrier Sense Input MII only ECOL Collision Detected Input MII only EMDC Management Data Clock Output EMDIO Management Data Input/Output I/O EF100 Force 100 Mbits/sec. Output High RMII only Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments |
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