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5962-03A0601QXC Datasheet(PDF) 9 Page - ATMEL Corporation |
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5962-03A0601QXC Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 50 page  9 AT7908E 4268D–AERO–11/09 Detailed Pin Description Internal Register Description MODE Input pin to select the operational mode of the interface: mode = 0 : 8 bits of the data bus multiplexed with the lowest 8 bits of the address(register mapped between 8000Hex and 804Chex) mode = 1 : 8 bits not multiplexed with the address data bus ( register mapped between 00 Hex and 4C Hex) CS Chip select pin to write or read the internal register. A high level on this pin enables the CPU to access the AT7908E. WR Pin to write the internal register. A low level on this pin enables the writing of the AT7908E register (if CS signal is HIGH). RD Pin to read the internal register. A low level on this pin enables the readout of the AT7908E register (if CS signal is HIGH). ALE Address-latch-enable. Used in mode=0. XTALIN Input pin for the clock. XTALIN, with XTALOUT, are the crystal connections for the internal oscillator. XTALOUT Input output pin. This pin could be used as the input, together with XTALIN, for the internal oscillator or as the clock output to drive the CPU. RESET Reset signal for the AT7908E. To reset the AT7908E, this signal must be set low. DATA<7:0> Bi-directional bus: Multiplexed data/address bus in the mode 0 or data bus in the mode1. ADDR<7:0> Highest input address in the mode0 or lowest input address in the mode 1. INT Output pin for the interrupt request to the MCU. This pin is active low (interrupt generation) and will be kept low until the MCU clears the interrupt request on AT7908E. CAN_TX Serial output pin to the CAN transceiver (dominant=‘0’, recessive=‘1’) CAN_RX Serial input from the CAN transceiver (dominant=‘0’, recessive=‘1’). SENA Input signal to enable the scan-test (with test = 1) or to put the AT7908E on power down mode (with test signal = 0). To use the AT7908E in normal functional mode, this signal must be logical 0. TEST Input signal to increase the testability. This pin will be used in the test modality. Test = 1 => test mode (used by the manufacturer that executes the test of the device. Test = 0 => functional mode ( if SENA =0) or power down mode ( if SENA =1). HATRIG Output signal that will be set high (duration of the pulse = 13 clock cycles) if the received message arbitration matches the TRIGGER_MATCH register (independently from the matching between the arbitration of the incoming message and the identifier of the message buffers). This pin could be used for the bus switching in a system with two physical buses (nominal and redundant). HASYNC Output signal that could be used to advise that the node started to transmit a message or started to receive a message (duration of the pulse = 13 clock cycles). Register Name Type R = read R/W = read/write Address Hex Register function ( bit7… bit0) SETUP_0 R/W 00 BPR1 BPR0 Gensync Tx Gensync Rx Errint Overint Rxint Txint SETUP_1 R/W 01 Disabled TXRM TXEM TMRMR TXDLC3 TXDLC1 TXDLC1 TXDLC0 SETUP_2 R/W 02 PS2_3 PS2_2 PS2_1 PS2_0 PS1_3 PS1_2 PS1_1 PS1_0 SETUP_3 R/W 03 RxClr Reset IntClr AbortTx Txreq RSJ2 RSJ1 RSJ0 SETUP_RX R/W 04 reserved reserved reserved Reserved reserved Rxclr3 Rxclr2 Rxclr1 |
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