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AT89LP216 Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT89LP216 Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 98 page  2 3621D–MICRO–10/09 AT89LP216 need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption. The AT89LP216 provides the following standard features: 2K bytes of In-System Programmable Flash memory, 128 bytes of RAM, up to 14 I/O lines, two 16-bit timer/counters, two PWM out- puts, a programmable watchdog timer, a full duplex serial port, a serial peripheral interface, an internal 8 MHz RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system. The two timer/counters in the AT89LP216 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may independently drive a pulse width modulation output. The I/O ports of the AT89LP216 can be independently configured in one of four operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode pro- vides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt using the general-purpose interrupt interface. The I/O pins of the AT89LP216 tolerate voltages higher than the device’s own power supply, up to 5.5V. When the device is supplied at 2.4V and all I/O ports receive 5.5V, the total back flowing current in all I/Os is less than 100 µA. 2. Pin Configuration 2.1 16-lead PDIP/SOIC/TSSOP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 (GPI5/MOSI) P1.5 (GPI7/SCK) P1.7 (GPI3/RST) P1.3 GND (GPI2) P1.2 (RXD) P3.0 (T0) P3.4 (XTAL1/INT0) P3.2 P1.6 (MISO/GPI6) P1.4 (SS/GPI4) P1.1 (AIN1/GPI1) P1.0 (AIN0/GPI0) VCC P3.1 (TXD) P3.5 (T1) P3.3 (INT1/XTAL2/CLKOUT) |
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