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AT89LP4052 Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT89LP4052 Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 94 page  4 3547J–MICRO–10/09 AT89LP2052/LP4052 4. Block Diagram 5. Memory Organization The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for pro- gram and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM which is divided into regions that may be accessed by different instruction classes. The AT89LP2052/LP4052 does not support external RAM. 5.1 Program Memory The AT89LP2052/LP4052 contains 2/4K bytes of on-chip In-System Programmable Flash mem- ory for program storage. The Flash memory has an endurance of at least 10,000 write/erase cycles. Section 23. “Programming the Flash Memory” on page 57 contains a detailed description on Flash Programming in ISP or Parallel Programming mode. The reset and interrupt vectors are located within the first 59 bytes of program memory (see Section 14. “Interrupts” on page 16). Constant tables can be allocated within the entire 2/4-Kbyte program memory address space for access by the MOVC instruction. Single Cycle 8051 CPU 2/4-Kbyte Flash 256-Byte RAM Port 3 Configurable I/O Port 1 Configurable I/O UART SPI Timer 0 Timer 1 Analog Comparator Watchdog Timer Configurable Oscillator CPU Clock Crystal or Resonator |
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