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AT28HC64B-70SU Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT28HC64B-70SU Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 17 page 9 0274L–PEEPR–2/3/09 AT28HC64B 17. Page Mode Write Waveforms(1)(2) Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 18. Chip Erase Waveforms tS = tH = 5 µs (min.) tW = 10 ms (min.) VH = 12.0 V ±0.5 V 16. Page Mode Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tWC Write Cycle Time (Use AT28HC64BF)) 2 ms tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 50 ns OE WE CE A0 -A12 DATA tAS VALID ADD VALID DATA tAH tDS tWP tWPH tDH tBLC tWC tS tW tH |
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