EN39LV010-45RJIP datasheet(8/36 Pages) EON

Part #	EN39LV010-45RJIP

Description	1 Megabit (128K x 8-bit ) 4 Kbyte Uniform Sector, CMOS 3.0 Volt-only Flash Memory

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Manufacturer	EON [Eon Silicon Solution Inc.]

Direct Link	http://www.essi.com.tw

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This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

8

EN39LV010

Rev. B, Issue Date: 2009/03/16

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data

protection against inadvertent writes as seen in the Command Definitions table. Additionally, the

following hardware data protection measures prevent accidental erasure or programming, which

might otherwise be caused by false system level signals during Vcc power up and power down

transitions, or from system noise.

Low VCC Write Inhibit

When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during

Vcc power up and power down. The command register and all internal program/erase circuits are

disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The

system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is

greater than VLKO.

Write Pulse “Glitch” protection

Noise pulses of less than 5 ns (typical) on OE , CE or W E do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a

write cycle, CE and W E must be a logical zero while OE is a logical one. If CE , W E , and OE are

all logical zero (not recommended usage), it will be considered a read.

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even

with CE = VIL, WE = VIL and OE = VIH, the device will not accept commands on the rising edge of

W E .

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