This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc.,

www.eonssi.com

or modifications due to changes in technical specifications.

4

EN25S40

Rev. A, Issue Date: 2009/04/28

SIGNAL DESCRIPTION

The EN25S40 support standard SPI and Dual SPI operation. Standard SPI instructions use the

unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising

edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read

data or status from the device on the falling edge CLK.

Dual SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the

device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is

deselected, the devices power consumption will be at standby levels unless an internal erase, program

or status register cycle is in progress. When CS# is brought low the device will be selected, power

consumption will increase to active levels and instructions can be written to and data read from the

device. After power-up, CS# must transition from high to low before a new instruction will be accepted.

HOLD (HOLD#)

The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought

low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be

ignored (don’t care). The HOLD# function can be useful when multiple devices are sharing the same

SPI signals.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register

Protect (SRP) bits, a portion or the entire memory array can be hardware protected.