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ICS844004-104 Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS844004-104 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 16 page ICS844004-104 FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER 10 ICS844004AK-104 REV. A SEPTEMBER 15, 2008 Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from the REF_CLK to ground. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 Ω across. If they are left floating, we recommend that there is no trace attached. 3.3V, 2.5V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100 Ω differential transmission line environment, LVDS drivers require a matched load termination of 100 Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination LVDS Driver R1 100 Ω – + 50 Ω 50 Ω 3.3V or 2.5V V DD 100 Ω Differential Transmission Line |
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