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874003AG-04 Datasheet(PDF) 3 Page - Integrated Device Technology |
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874003AG-04 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 15 page ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-04 REVISION A NOVEMBER 4, 2009 3 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Output Enable Function Table Number Name Type Description 1, 20 QA1, nQA1 Output Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output Differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Input Pulldown Frequency select pin for QAx, nQAx and QB0, nQB0 outputs. LVCMOS/LVTTL interface levels. 7 nc Unused No connect. 8VDDA Power Analog supply pin. 10 VDD Power Core supply pin. 11 OEA Input Pullup Output enable pin for QA pins. When HIGH, the QAx, nQAx outputs are active. When LOW, the QAx, nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground. 15 OEB Input Pullup Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are active. When LOW, the QB0, nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 17, 18 nQB0, QB0 Output Differential output pair. LVDS interface levels. Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4pF RPULLUP Input Pullup Resistor 51 k Ω RPULLDOWN Input Pulldown Resistor 51 k Ω Inputs Outputs OEx Qx[0:1], nQx[0:1] 0 Hi-Impedance 1 Enabled |
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