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ICS871004AGI-04LFT Datasheet(PDF) 9 Page - Integrated Device Technology |
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ICS871004AGI-04LFT Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 15 page IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 9 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY APPLICATION INFORMATION Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. V_REF R1 1K C1 0.1u R2 1K Single Ended Clock Input CLK nCLK VDD POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter per- formance, power supply isolation is required. The ICS871004I- 04 provides separate power supplies to isolate any high switch- ing noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10 Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. FIGURE 1. POWER SUPPLY FILTERING 10 Ω V DDA 10 μF .01 μF 3.3V .01 μF V DD INPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: DIFFERENTIAL OUTPUTS All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. |
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