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TLE8262E Datasheet(PDF) 11 Page - Infineon Technologies AG |
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TLE8262E Datasheet(HTML) 11 Page - Infineon Technologies AG |
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11 / 93 page  Data Sheet 11 Rev. 1.0, 2009-03-31 TLE8262E State Machine 4.2 State Machine Description The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash, Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations, accessed via two external pins and one SPI bit. 4.2.1 Configuration Description Table 1 provides descriptions and conditions for entry to the different configurations of the SBC. In SBC SW Development Mode, Config 1 to 4 are accessible. 4.2.2 SBC Power ON Reset (POR) At V S > VUVON, the SBC starts to operate, by reading the test pin and then by turning ON Vcc1µC. When Vcc1µC reaches the reset threshold V RT1, the reset output remains activated for tRD1 and the SBC enters then the Init Mode. In the event that V s decreases below VUVOFF, the device is completely disabled. For more details on the disable behavior of the SBC blocks, please refer to the chapter specific to each block. 4.2.3 SBC Init Mode At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after powering-up, waits for the microcontroller to finish its startup and initialization sequences. V cc2/3 are OFF and the Watchdog is configurable but not active. CAN and LIN modules are inactive and Limp Home output is inactive. From this transition mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal or Software Flash Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not send the device to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it will enter into SBC Restart Mode and activate the Limp Home output. Note: In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the watchdog the first time and sets the required watchdog settings. Table 1 SBC Configuration Configuration Description Test pin INT Pin WD to LH bit config 0 Software Development Mode 0V n.a n.a config 1 After missing the WD trigger for the first time, the state of V cc1µC remain unchanged, LH pin is active, SBC in Restart Mode Open / V S External pull-up 0 config 2 After missing the WD trigger for the first time, V cc1µC turns OFF, LH pin is active, SBC in Fail-Safe Mode No ext. pull-up 0 config 3 After missing the WD trigger for the second time, the state of V cc1µC remain unchanged, LH pin is active, SBC in Restart Mode External pull-up 1 config 4 After missing the WD trigger for the second time, V cc1µC turns OFF, LH pin is active, SBC in Fail-Safe Mode No ext. pull-up 1 |
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