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8430S07AKILF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 8430S07AKILF
Description  Clock Generator for Cavium Processors
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8430S07AKILF Datasheet(HTML) 8 Page - Integrated Device Technology

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ICS8430S07AKI REVISION A SEPTEMBER 3, 2009
8
©2009 Integrated Device Technology, Inc.
ICS8430S07I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at fMAX unless noted otherwise.
NOTE 1: Refer to the phase noise plot.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: All outputs running at corresponding fMAX.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
QA/nQA
DDR_SEL[1:0] = 00
133.333
MHz
QA/nQA
DDR_SEL[1:0] = 01
100
MHz
QA/nQA
DDR_SEL[1:0] = 10
83.333
MHz
QA/nQA
DDR_SEL[1:0] = 11
125
MHz
QB
CORE_SEL = 0
50
MHz
QB
CORE_SEL = 1
33.333
MHz
QC
PCI_SEL[1:0] = 00
133.333
MHz
QC
PCI_SEL[1:0] = 01
100
MHz
QC
PCI_SEL[1:0] = 10
66.667
MHz
QC
PCI_SEL[1:0] = 11
33.333
MHz
QD
125
MHz
QREF[0:2]
25
MHz
tsk(b)
Bank Skew;
NOTE 2, 4
QREF[0:2]
35
ps
tsk(pp)
Part-to-Part Skew;
NOTE 3, 4
QREF[0:2]
400
ps
tjit(cc)
Cycle-to-Cycle Jitter;
NOTE 4, 5
QB, QC,
270
ps
QA/nQA
measured at crosspoint
95
ps
QD
200
ps
tjit(per)
Period Jitter (pk-pk);
NOTE 4
QA/nQA
measured at crosspoint
-90
90
ps
tjit(hper)
Half-period Jitter
(pk-pk)
QA/nQA
measured at crosspoint
-90
90
ps
tjit(Ø)
RMS Phase Jitter,
(Random); NOTE 1
QREF[0:2]
25MHz (10kHz to 5MHz)
0.73
ps
QD
125MHz (1.875MHz to 20MHz)
0.78
ps
tR / tF
Output
Rise/Fall Time
QB
20% to 80%
100
450
ps
QA/nQA
100
300
ps
QC, QREF[0:2]
100
450
ps
QD
100
450
ps
odc
Output Duty Cycle
QA/nQA
49
51
%
QB, QC, QD,
QREF[0:2]
45
55
%


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