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ICS1893BKT Datasheet(PDF) 7 Page - Integrated Device Technology |
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ICS1893BKT Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 138 page Table of Contents ICS1893BF, Rev. E, 8/11/09 August, 2009 7 ICS1893BF Data Sheet Rev. E - Release Copyright © 2009, IDT, Inc. All rights reserved. Table of Contents Section Title Page 7.14 Register 19: Extended Control Register 2 .............................................................87 7.14.1 Node Configuration (bit 19.15) ...............................................................................88 7.14.2 Hardware/Software Priority Status (bit 19.14) ........................................................88 7.14.3 Remote Fault (bit 19.13) ........................................................................................88 7.14.4 ICS Reserved (bits 19.12:10) .................................................................................88 7.14.5 Auto-MDI/MDIX (bits 19. 9:13)................................................................................88 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) .....................................................89 7.14.7 ICS Reserved (bits 19.6:1) .....................................................................................89 7.14.8 Automatic 100Base-TX Power-Down (bit 19.0) .....................................................89 Chapter 8 Pin Diagram, Listings, and Descriptions ....................................................................... 90 8.1 ICS1893BF Pin Diagram ........................................................................................90 8.2 ICS1893BF Pin Descriptions .................................................................................91 8.2.1 Transformer Interface Pins .....................................................................................92 8.2.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .............................92 8.2.3 Configuration Pins...................................................................................................96 8.2.4 MAC Interface Pins .................................................................................................97 8.2.5 Ground and Power Pins........................................................................................101 8.3 ICS1893BK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) ..............................102 8.3.1 ICS1893BK Pin Descriptions ................................................................................103 8.3.2 Transformer Interface Pins ...................................................................................104 8.3.3 Ground and Power Pins........................................................................................105 Chapter 9 DC and AC Operating Conditions................................................................................. 106 9.1 Absolute Maximum Ratings .................................................................................106 9.2 Recommended Operating Conditions ..................................................................106 9.3 Recommended Component Values .....................................................................107 9.4 DC Operating Characteristics ..............................................................................108 9.4.1 DC Operating Characteristics for Supply Current ................................................108 9.4.2 DC Operating Characteristics for TTL Inputs and Outputs ..................................108 9.4.3 DC Operating Characteristics for REF_IN ...........................................................109 9.4.4 DC Operating Characteristics for Media Independent Interface ..........................109 9.5 Timing Diagrams ..................................................................................................110 9.5.1 Timing for Clock Reference In (REF_IN) Pin .......................................................110 9.5.2 Timing for Transmit Clock (TXCLK) Pins .............................................................111 9.5.3 Timing for Receive Clock (RXCLK) Pins ..............................................................112 9.5.4 100M MII: Synchronous Transmit Timing .............................................................113 9.5.5 10M MII: Synchronous Transmit Timing ..............................................................114 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing ...............115 9.5.7 MII Management Interface Timing .......................................................................116 9.5.8 10M Media Independent Interface: Receive Latency ...........................................117 9.5.9 10M Media Independent Interface: Transmit Latency...........................................118 9.5.10 100M/MII Media Independent Interface: Transmit Latency...................................119 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)................120 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................121 9.5.13 100M MII Media Independent Interface: Receive Latency....................................122 |
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