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ICS854S204AGILF Datasheet(PDF) 11 Page - Integrated Device Technology |
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ICS854S204AGILF Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 19 page IDT™ / ICS™ LVDS, LVPECL FANOUT BUFFER 11 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. Both V SWING and VOH must meet the VPP and V CMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER PCLK/nPCLK 2.5V Zo = 60 Ohm SSTL HiPerClockS PCLK nPCLK R2 120 3.3V R3 120 Zo = 60 Ohm R1 120 R4 120 2.5V FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER HiPerClockS PCLK nPCLK PCLK/nPCLK 3.3V R2 50 R1 50 3.3V Zo = 50 Ohm CML 3.3V Zo = 50 Ohm 3.3V HiPerClockS PCLK nPCLK R2 84 R3 125 Input Zo = 50 Ohm R4 125 R1 84 LVPECL 3.3V 3.3V Zo = 50 Ohm 3.3V R5 100 - 200 3.3V 3.3V HiPerClockS PCLK nPCLK R1 125 PCLK/nPCLK R2 125 R3 84 C1 C2 Zo = 50 Ohm R4 84 Zo = 50 Ohm R6 100 - 200 3.3V LVPECL FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 3.3V CML Built-In Pullup R1 100 PCLK nPCLK HiPerClockS PCLK/nPCLK Zo = 50 Ohm Zo = 50 Ohm |
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