ICS840S06I

CLOCK GENERATOR FOR CAVIUM PROCESSORS

PRELIMINARY

IDT™ / ICS™ CLOCK GENERATOR

3

ICS840S06AKI REV. AI JULY 10, 2008

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Number

Name

Type

Description

1, 15

Power

Core supply pins.

2

nPLL_SEL

Input

Pulldown

PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, deselects

the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.

3,

4

XTAL_IN,

XTAL_OUT

Input

Parallel resonant crystal interface.

XTAL_OUT is the output, XTAL_IN is the input.

5

nXTAL_SEL

Input

Pulldown

Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK)

input when HIGH. LVCMOS/LVTTL interface levels.

6

CLK

Input

Pulldown

Non-inverting differential clock input.

7

nCLK

Input

Pullup/

Pulldown

8, 20, 21, 27

GND

Power

Power supply ground.

9,

10

PCI_SEL1,

PCI_SEL0

Input

Pulldown

Selects the PCI/PCI-X reference clock output frequency. See Table 3B.

LVCMOS/LVTTL interface levels.

11, 12, 13, 14

nc

Unused

No connect.

16

Power

Analog supply pin.

17

Power

Bank A output supply pin. 3.3 V or 2.5V supply.

18, 23, 26, 29,

30, 31

QA, QB, QC,

QREF2,

QREF1, QREF0

Output

Single-ended outputs. LVCMOS/LVTTL interface levels.

19

nOE_REF

Input

Pulldown

Active LOW output enable. When logic HIGH, the outputs are in high

impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/

LVTTL interface levels.

22

CORE_SEL

Input

Pulldown

Selects the processor core clock output frequency. The output frequency is

50MHz when LOW, and 33.333MHz when HIGH. See Table 3A.

LVCMOS/LVTTL interface levels.

24

Power

Bank B output supply pin. 3.3 V or 2.5V supply.

25

Power

Bank C output supply pin. 3.3 V or 2.5V supply.

28, 32

Power

REF bank output supply pins. 3.3 V or 2.5V supply.