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December 5, 2008

IDT79RC4640™

System Control Coprocessor (CP0)

The system control coprocessor in the MIPS architecture is respon-

sible for the virtual to physical address translation and cache protocols,

the exception control system, and the diagnostics capability of the

processor. In the MIPS architecture, the system control coprocessor

(and thus the kernel software) is implementation dependent.

In the RC4640, significant changes in CP0 relative to the RC4600

have been implemented. These changes are designed to simplify

memory management, facilitate debug, and speed real-time processing.

System Control Coprocessor Registers

The RC4640 incorporates all system control co-processor (CP0)

registers on-chip. These registers provide the path through which the

virtual memory system’s address translation is controlled, exceptions

are handled, and operating modes are controlled (kernel vs. user mode,

interrupts enabled or disabled, cache features). In addition, the RC4640

includes registers to implement a real-time cycle counting facility, which

aids in cache diagnostic testing, assists in data error detection, and facil-

itates software debug. Alternatively, this timer can be used as the

operating system reference timer, and can signal a periodic interrupt.

Table 3 shows the CP0 registers of the RC4640.

Number

Name

Function

0

IBase

Instruction address space base

1

IBound

Instruction address space bound

2

DBase

Data address space base

3

DBound

Data address space bound

4-7, 10, 20-25,

29, 31

-

Not used

8

BadVAddr

Virtual address on address exceptions

9

Count

Counts every other cycle

11

Compare

Generate interrupt when Count = Compare

12

Status

Miscellaneous control/status

13

Cause

Exception/Interrupt information

14

EPC

Exception PC

15

PRId

Processor ID

16

Config

Cache and system attributes

17

CAlg

Cache attributes for the 8 512MB regions of the

virtual address space

18

IWatch

Instruction breakpoint virtual address

19

DWatch

Data breakpoint virtual address

26

ECC

Used in cache diagnostics

27

CacheErr

Cache diagnostic information

28

TagLo

Cache index information

30

ErrorEPC

CacheError exception PC

Table 3 RC4640 CPO Registers

Operation Modes

The RC4640 supports two modes of operation: user mode and

kernel mode. Kernel mode operation is typically used for exception

handling and operating system kernel functions, including CP0 manage-

ment and access to IO devices. In kernel mode, software has access to

the entire address space and all of the co-processor 0 registers, and

can select whether to enable co-processor 1 accesses. The processor

enters kernel mode at reset, and whenever an exception is recognized.

User mode is typically used for applications programs. User mode

accesses are limited to a subset of the virtual address space, and can

be inhibited from accessing CP0 functions.

Virtual-to-Physical Address Mapping

The 4GB virtual address space of the RC4640 is shown in Figure 1.

The 4 GB address space is divided into addresses accessible in either

kernel or user mode (kuseg), and addresses only accessible in kernel

mode (kseg2:0).

The RC4640 supports the use of multiple user tasks sharing

common virtual addresses, but mapped to separate physical addresses.

This facility is implemented via the “base-bounds” registers contained in

CP0.

When a user virtual address is asserted (load, store, or instruction

fetch), the RC4640 compares the virtual address with the contents of

the appropriate “bounds” register (instruction or data). If the virtual

0xFFFFFFFF

0xC0000000

Kernel virtual address space

(kseg2)

Unmapped, 1.0 GB

0xBFFFFFFF

0xA0000000

Uncached kernel physical address space

(kseg1)

Unmapped, 0.5GB

0x9FFFFFFF

0x80000000

Cached kernel physical address space

(kseg0)

Unmapped, 0.5GB

0x7FFFFFF

0x00000000

User virtual address space

(useg)

Mapped, 2.0GB

Figure 1 Mode Virtual Addressing (32-bit mode)