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COMMERCIALTEMPERATURERANGE

IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO

512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9

FEBRUARY 5, 2009

Single Device Mode, this pin acts as the retransmit input. The Single Device

Mode is initiated by grounding the Expansion In (

XI).

The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit

data when the Retransmit Enable control (

RT)inputispulsedlow. Aretransmit

operation will set the internal read pointer to the first location and will not affect

the write pointer. Read Enable (

R) and Write Enable (W) must be in the high

stateduringretransmitfortheIDT72V81/72V82/72V83/72V84/72V85respec-

tively.Thisfeatureisusefulwhenlessthan512/1,024/2,048/4,096/8,192writes

areperformedbetweenresets.Theretransmitfeatureisnotcompatiblewiththe

Depth Expansion Mode and will affect the Half-Full Flag (

HF), depending on

the relative locations of the read and write pointers.

EXPANSION IN (

XI )

This input is a dual-purpose pin. Expansion In (

XI) is grounded to indicate

an operation in the single device mode. Expansion In (

XI) is connected to

Expansion Out (

XO) of the previous device in the Depth Expansion or Daisy

Chain Mode.

OUTPUTS:

FULL FLAG (

FF )

The Full Flag (

FF)willgolow,inhibitingfurtherwriteoperation,whenthewrite

pointer is one location less than the read pointer, indicating that the device is full.

If the read pointer is not moved after Reset (

RS), the Full-Flag (FF) will go low

after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes

for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the

IDT72V85.

EMPTY FLAG (

EF )

The Empty Flag (

EF) will go low, inhibiting further read operations, when

the read pointer is equal to the write pointer, indicating that the device is

empty.

EXPANSION OUT/HALF-FULL FLAG (

XO/HF )

This is a dual-purpose output. In the single device mode, when Expan-

sion In (

XI)isgrounded,thisoutputactsasanindicationofahalf-fullmemory.

After half of the memory is filled and at the falling edge of the next write

operation, the Half-Full Flag (

HF) will be set low and will remain set until the

difference between the write pointer and read pointer is less than or equal

toonehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(

HF)isthenreset

by using rising edge of the read operation.

IntheDepthExpansionMode,ExpansionIn(

XI)isconnectedtoExpansion

Out (

XO) of the previous device in the Daisy Chain by providing a pulse to the

next device when the previous device reaches the last location of memory.

Data outputs for 9-bit wide data. This data is in a high impedance

condition whenever Read (

R) is in a high state.

SIGNAL DESCRIPTIONS

INPUTS:

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

RS )

ResetisaccomplishedwhenevertheReset(

RS)inputistakentoalowstate.

During reset, both internal read and write pointers are set to the first location.

A reset is required after power up before a write operation can take place. Both

the Read Enable (

R) and Write Enable ( W) inputs must be in the high

edge of

RS. Half-Full Flag ( HF ) will be reset to high after Reset ( RS ).

WRITE ENABLE (

W )

A write cycle is initiated on the falling edge of this input if the Full Flag (

FF)

isnotset.Dataset-upandholdtimesmustbeadheredtowithrespecttotherising

edge of the Write Enable (

W).DataisstoredintheRAMarraysequentiallyand

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of the next write

operation, the Half-Full Flag (

HF) will be set to low and will remain set until the

difference between the write pointer and read pointer is less than or equal to

one half of the total memory of the device. The Half-Full Flag (

HF)isthenreset

by the rising edge of the read operation.

Topreventdataoverflow,theFullFlag(

FF)willgolow,inhibitingfurtherwrite

operations. Upon the completion of a valid read operation, the Full Flag (

FF)

internal write pointer is blocked from

W,soexternalchangesinWwillnotaffect

the FIFO when it is full.

READ ENABLE (

R )

A read cycle is initiated on the falling edge of the Read Enable (

R)provided

theEmptyFlag(

EF)isnotset.ThedataisaccessedonaFirst-In/First-Outbasis,

independentofanyongoingwriteoperations.AfterReadEnable(

R)goeshigh,

next Read operation. When all data has been read from the FIFO, the Empty

Flag (

EF) will go low, allowing the “final” read cycle but inhibiting further read

operations with the data outputs remaining in a high impedance state. Once a

valid write operation has been accomplished, the Empty Flag (

EF)willgohigh

read pointer is blocked from

RsoexternalchangesinRwillnotaffecttheFIFO

when it is empty.

FIRST LOAD/RETRANSMIT (

FL/RT )

This is a dual-purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first loaded (see Operating Modes). In the