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LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 61 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS – CLOCK) Notes: 1. Both the clock and the strobe are drawn on different time scales. VSS Hol d slew rate falling signal Hol d slew rate rising signal ∆TR ∆TF = = VCCQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX Nominal slew rate DC to VREF region DQS DQS# CK# CK t IS t IH t IS t IH DC to VREF region Nominal slew rate VREF(DC) - VIL(DC) MAX ∆TR VIH(DC) MIN - V REF(DC) ∆TF |
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