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CK CK# t AON VSSQ DQ, DM DQS, DQS# Begin point: Rising edge of CK - CK# defined by the end point of ODTL on VSW1 End point: Extrapolated point at VSSQ TSW1 TSW2 CK CK# VCCQ/2 t AOF End point: Extrapolated point at VRTT_NOM VRTT_NOM VSSQ t AON t AOF VSW2 VSW2 VSW1 TSW1 TSW1 Begin point: Rising edge of CK - CK# defined by the end point of ODTL off LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 38 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product PACKAGE OUTLINE DIMENSIONS Symbol Begin Point Definition End Point Definition Figure tAON tAOF tAONPD tAOFPD tADC TABLE 33: ODT TIMING DEFINITIONS Figure 25 on page 60 Figure 25 on page 60 Figure 26 on page 61 Figure 26 on page 61 Figure 27 on page 62 Extrapolated point at VssQ Extrapolated point at VRTT_NORM Extrapolated point at VssQ Extrapolated point at VRTT_NOM Extrapolated points at VRTT_WR and VRTT_NOM Rising edge of CK-CK\ defined by the end point of ODTL on Rising edge of CK-CK\ defined by the end point of ODTL off Rising edge of CK-CK\ with ODT first being registered HIGH Rising edge of CK-CK\ with ODT first being registered LOW Rising edge of CK-CK\ defined by the end point of ODTLCNW, ODTLCWN4, or ODTLCWN8 PACKAGE OUTLINE DIMENSIONS Parameter RTT_NORM Setting RTT_WR_Setting VSW1 VSW2 tAON tAOF tAONPD tAOFPD tADC TABLE 34: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS 100mV 200mV 100mV 200mV 100mV 200mV 100mV 200mV 300mV 50mV 100mV 50mV 100mV 50mV 100mV 50mV 100mV 200mV n/a n/a n/a n/a n/a n/a n/a n/a RZQ/2 (120Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/4 (60Ω) RZQ/12 (20Ω) RZQ/12 (20Ω) Measured FIGURE 16 - tAON AND tAOF DEFINITIONS ODT TIMING DEFINITIONS |
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