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LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 75 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE Command T0 T1 Ta0 Ta1 Tb0 Tc0 7 6 Td0 Td1 Te0 Te1 Tf0 CK CK# ODT9 Vali d1 Don ’t Care Vali d1 SRE3 NOP MRS2 NOP SRX4 MRS5 Vali d1 NOP NOP Indicates a Break in Time Scale t MOD t CKSRE t MOD t XS t CKESR CKE t CKSRX8 NOTES: Any valid command. 1. Disable DLL by setting MR1[0] to “1.” 2. Wait 3. tXS, then set MR1[0] to “0” to enable DLL. Wait 4. tMRD, then set MR0[8] to “1” to begin DLL RESET. Wait 5. tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait 6. tMOD, any valid command. Starting with the idle state. 7. Change frequency. 8. Clock must be stable at least 9. tCKSRX. Static LOW in case R 10. TT _NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 44 on page 100). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to “0” to enable the DLL. Wait tMRD, then set MR0[8] to “1” to enable DLL RESET. 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met as well. |
