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FWLF1524P2V61 Datasheet(PDF) 2 Page - Finisar Corporation.

Part # FWLF1524P2V61
Description  4 Gigabit RoHS Compliant CWDM SFP Transceiver
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Manufacturer  FINISAR [Finisar Corporation.]
Direct Link  http://www.finisar.com/home.php
Logo FINISAR - Finisar Corporation.

FWLF1524P2V61 Datasheet(HTML) 2 Page - Finisar Corporation.

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FWLF1524P2Vxx SFP Product Specification – October 2006
F i n i s a r
© Finisar Corporation October 31, 2006 Rev C Preliminary
Page 2
I.
Pin Descriptions
Pin
Symbol
Name/Description
Ref.
1
VEET
Transmitter Ground (Common with Receiver Ground)
1
2
TFAULT
Transmitter Fault. Not supported.
3
TDIS
Transmitter Disable. Laser output disabled on high or open.
2
4
MOD_DEF(2)
Module Definition 2. Data line for Serial ID.
3
5
MOD_DEF(1)
Module Definition 1. Clock line for Serial ID.
3
6
MOD_DEF(0)
Module Definition 0. Grounded within the module.
3
7
Rate Select
Open or Low =
High =
1.063 Gb/s or 2.125 Gb/s Fibre Channel, 1.25 Gb/s
Gigabit Ethernet (Low Bandwidth)
2.125 or 4.25 Gb/s Fibre Channel (High Bandwidth)
4
8
LOS
Loss of Signal indication. Logic 0 indicates normal operation.
5
9
VEER
Receiver Ground (Common with Transmitter Ground)
1
10
VEER
Receiver Ground (Common with Transmitter Ground)
1
11
VEER
Receiver Ground (Common with Transmitter Ground)
1
12
RD-
Receiver Inverted DATA out. AC Coupled
13
RD+
Receiver Non-inverted DATA out. AC Coupled
14
VEER
Receiver Ground (Common with Transmitter Ground)
1
15
VCCR
Receiver Power Supply
16
VCCT
Transmitter Power Supply
17
VEET
Transmitter Ground (Common with Receiver Ground)
1
18
TD+
Transmitter Non-Inverted DATA in. AC Coupled.
19
TD-
Transmitter Inverted DATA in. AC Coupled.
20
VEET
Transmitter Ground (Common with Receiver Ground)
1
Notes:
1.
Circuit ground is internally isolated from chassis ground.
2.
Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.
3.
Should be pulled up with 4.7k - 10 kohms on host board to a voltage between 2.0V and 3.6V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4.
Specific information when selecting line rate:
Rate selection is done in accordance with SFF
Committee SFF-8079 Draft, Rev.1.6, Table 3. Note that rate select can also be set through 2-wire bus
in accordance with SFF-8472
6 at Bit 3, Byte 110, Address A2h (note: writing ‘1’ selects full bandwidth
operation). Rate select is the logic OR of the input state of Rate Select Pin and 2-wire bus. Non Rate
Selectable version can operate at 1x, 2x, 4x Fibre Channel independent of rate select pin setting.
5.
LOS is open collector output. Should be pulled up with 4.7k – 10 kohms on host board to a voltage
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
VeeT
VeeR
VeeR
TD-
TD+
RD+
RD-
VccT
VccR
VeeT
VeeR
TXFault
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
LOS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Towards
ASIC
Towards
Bezel
TX Disable
VeeR
Pinout of Connector Block on Host Board


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