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UCD90120 Datasheet(PDF) 5 Page - Texas Instruments |
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UCD90120 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 40 page  PMBus/SMBus/I 2C I 2C/SMBus/PMBus TIMING REQUIREMENTS Start Stop Clk ACK Clk ACK PMB_Clk PMB_Data TLOW:SEXT TLOW:MEXT TLOW:MEXT TLOW:MEXT UCD90120 www.ti.com.......................................................................................................................................................................................... SLVS966 – SEPTEMBER 2009 The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus is shown below. TA = –40°C to 85°C, 3.0V < VDD < 3.6V; Typical values at TA = 25°C and VCC = 2.5V (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty 10 1000 kHz cycle FI2C I2C operating frequency Slave mode, SCL 50% duty cycle 10 1000 kHz t(BUF) Bus free time between start and stop 4.7 µs t(HD:STA) Hold time after (repeated) start 0.26 µs t(SU:STA) Repeated start setup time 0.26 µs t(SU:STO) Stop setup time 0.26 µs t(HD:DAT) Data hold time Receive Mode 0 ns t(SU:DAT) Data setup time 50 ns t(TIMEOUT) Error signal/detect See(1) 35 ms t(LOW) Clock low period 0.5 µs t(HIGH) Clock high period See (2) 0.26 50 µs t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms tFALL Clock/data fall time See (4) 120 ns tRISE Clock/data rise time See (5) 120 ns (1) The device times out when any clock low exceeds t(TIMEOUT). (2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). (3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15) (5) Fall time tf = 0.9VDD to (VILMAX – 0.15) Figure 1. I2C/SMBus Timing Diagram Figure 2. Bus Timing in Extended Mode Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s) :UCD90120 |
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