Integrator

ResetSample

(SHR)

SignalSample

(SHS)

FiltBypass

FiltBypass

LPF

LPF

SHR

SHS

+

-

SHS-SHR

CDS

IRST

PIN FUNCTIONS (continued)

PIN

I/O

DESCRIPTION

NUMBER

NAME

49, 51, 52,

VSS

I

Ground for device power supply

54, 59, 62,

65, 71, 73,

74, 76, 79,

80, 82, 85,

86, 90, 91,

99, 101, 102,

103, 107,

109, 110

TFT CHARGE INJECTION COMPENSATION

72

DF-SM

I

Digital control to dump compensation charge on integrator capacitor; this is useful to nullify the

effect of pixel TFT charge injection.

56

VT-A

I

External voltage to control the amount of charge dump for TFT charge injection compensation.

Charge dump = (V-voltage at 'EXT_C')*0.857 pC where V is external voltage at pins 56, 57. Short

pins 56 and 57 externally and apply external voltage for charge injection compensation.

57

VT-B

I

NC PINS

58, 111

These pins should be connected to VSS.

DESCRIPTIONS AND TIMING DIAGRAMS

Figure 1. Integrator Channel Schematic

Figure 1 shows the typical schematic of an integrator channel. As shown, each integrator has a reset (IRST)

switch which resets the integrator output to the 'reset-level'. The device integrates input current while this switch

is open. There are two sample and hold circuits connected to each integrator output. SHR samples integrator

reset level output and SHS samples integrator output post integration of signal charge. The device subtracts the

SHR sample from the SHS sample. The difference is then available at device output in a differential format. This

action is called 'Correlated Double Sampling' (CDS). CDS removes integrator offset and low frequency noise

from device output.

Each sample and hold has a built-in low pass filter. This filter limits sampling bandwidth so as to limit sampled

noise to an acceptable level. Detailed functioning of individual blocks is described further with timing diagrams.

8

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