TIMING REQUIREMENTS

PARAMETER

MIN

TYP

MAX

UNIT

SAMPLING AND CONVERSION RELATED

t-scan

Scan time, See Figure 1, Figure 7

28.3

µSec

2

t1

IRST, SHR, SHS, STI high duration, See Figure 1, Figure 7

30

nSec

t2

Setup time, STI falling edge to first clock rising edge, See Figure 1, Figure 7

30

nSec

t2

Setup time, IRST falling edge to first clock rising edge, See Figure 1, Figure 7

30

nSec

t3

400

nSec

t4

Delay time, SHR rising edge to INTG rising edge, See Figure 1, Figure 7

30

nSec

t5

INTG high duration (TFT on time), See Figure 1, Figure 7

14

µSec

t6

Delay time, INTG falling edge to SHS rising edge, See Figure 1, Figure 7

4.5

µSec

t7

Delay time, SHS rising edge to IRST rising edge, See Figure 1

30

nSec

t8

Delay time, SHS rising edge to STI rising edge, See Figure 1, Figure 7

30

nSec

t9

Hold time, STI falling edge to IRST falling edge, See Figure 1, Figure 7

10

nSec

In sequential mode

1

15

Clock (CLK) frequency

MHz

In simult mode

0.25

3.75

OUTP or OUTM settling time to 16 bit accuracy with 30 pF load and full scale

375

nSec

step

OUTP or OUTM settling time to 16 bit accuracy with 15 pF load and full scale

250

nSec

step

(1)

See max specification for t5 and minimum specification for CLK frequency. Also see the section Running the Device at Higher Scan

Time.

(2)

There is no real limit on maximum integration time, however as integration time increases the offset value changes due to integration of

leakage current (2 pA typical) also the 1/f noise contribution to output increases, refer to the typical noise numbers at 14 and 270 µSec

integration time in the Specifications table and also see Figure 28 .

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