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MAX8649 Datasheet(PDF) 2 Page - Maxim Integrated Products |
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MAX8649 Datasheet(HTML) 2 Page - Maxim Integrated Products |
2 / 31 page 1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. IN1, IN2 to AGND ..................................................-0.3V to +6.0V VDD to AGND.........................................................-0.3V to +4.0V LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (VIN1 + 0.3V) SCL, SDA, SYNC to AGND.........................-0.3V to (VDD + 0.3V) PGND, SNS- to AGND...........................................-0.3V to +0.3V RMS LX Current ..............................................................1800mA Continuous Power Dissipation (TA = +70°C) 16-Bump WLP 0.5mm Pitch (derate 13mW/°C above +70°C) ............................1040mW Operating Temperature Range ...........................-40°C to +85°C Junction to Ambient Thermal Resistance ( θJA) (Note 1)..76°C/W Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Bump Temperature (soldering, reflow) ............................+260°C PARAMETER CONDITIONS MIN TYP MAX UNITS IN1, IN2 Operating Range 2.5 5.5 V VDD Operating Range 1.8 3.6 V VDD Undervoltage Lockout (UVLO) Threshold VDD falling 0.54 0.865 1.35 V VDD UVLO Hysteresis 50 mV IN_ Undervoltage Lockout (UVLO) Threshold VIN falling 2.10 2.15 2.20 V IN_ UVLO Hysteresis 70 mV TA = +25°C 0.01 1 VDD Shutdown Supply Current VIN1 = VIN2 = 5.5V, EN = VDD = AGND TA = +85°C 0.01 µA TA = +25°C 0.25 1 IN1, IN2 Shutdown Supply Current VIN1 = VIN2 = 5.5V, EN = VDD = AGND TA = +85°C 0.25 µA TA = +25°C 0.35 1 IN1, IN2 Standby Supply Current VIN1 = VIN2 = 5.5V, SCL = SDA = VDD, EN = AGND, I 2C ready TA = +85°C 0.35 µA TA = +25°C 0.02 1 VDD Standby Supply Current VIN1 = VIN2 = VDD = 3.6V, SCL = SDA = VDD, EN = AGND, I 2C ready TA = +85°C 0.02 µA LOGIC INTERFACE EN, VID0, VID1 1.4 Logic Input High Voltage (VIH) VIN1 = VIN2 = 2.5V to 5.5V, VDD = 1.8V to 3.6V SYNC, SCL, SDA 0.7 x VDD V EN, VID0, VID1 0.4 Logic Input Low Voltage (VIL) VIN1 = VIN2 = 2.5V to 5.5V, VDD = 1.8V to 3.6V SYNC, SCL, SDA 0.3 x VDD V TA = +25°C -1 0.01 +1 SDA, SCL, SYNC Logic Input Current VIL = 0V or VIH = 3.6V, EN = AGND TA = +85°C 0.01 µA Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four- layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. |
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