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AT91SAM7X512 Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT91SAM7X512 Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 45 page  NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set • Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) • Single Cycle Access at Up to 30 MHz in Worst Case Conditions • Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed • Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms • 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit • Fast Flash Programming Interface for High Volume Production • Internal High-speed SRAM, Single-cycle Access at Maximum Speed – 128 Kbytes (AT91SAM7X512) – 64 Kbytes (AT91SAM7X256) – 32 Kbytes (AT91SAM7X128) • Memory Controller (MC) – Embedded Flash Controller, Abort Status and Misalignment Detection • Reset Controller (RSTC) – Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector – Provides External Reset Signal Shaping and Reset Source Status • Clock Generator (CKGR) – Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL • Power Management Controller (PMC) – Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode – Four Programmable External Clock Signals • Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention – Mode for General Purpose 2-wire UART Serial Communication • Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter • Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Product Description AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 Preliminary Summary 6120FS–ATARM–17-Feb-09 |
Similar Part No. - AT91SAM7X512_09 |
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Similar Description - AT91SAM7X512_09 |
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