Integrated Silicon Solution, Inc.

7

Rev. A

05/14/09

72 Mb (2M x 36 & 4M x 18)

QUADP (Burst of 4) Synchronous SRAMs

The Timing Reference Diagram for Truth Table on page

8 is helpful in understanding the clock and write truth

tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read

and write commands are issued at the beginning of cycle “t”.

State Diagram

Power-Up

Write NOP

Load New

Write Address

DDR

-II Write

Read NOP

Load New

Read Address

Read

Write

Read

Write

Read

Write

Read

Write

Notes: 1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst addresses are

2. Read refers to read active status with R = low. Read refers to read inactive status with R = high.

5. State machine control timing sequence is controlled by K.

4. The read and write state machines can be active simultaneously.

3. Write refers to write active status with W = low. Write refers to write inactive status with W = high.

Increment

Read Address

Increment

Write Address

DDR

-II Read

Always

Always

D count = 2

D count = 0

D count = 0

D count =

D count + 1

D count =

D count + 1

D count = 2

D count = 2

D count = 2

Always

Always

Write

D count = 1

Read

D count = 1

.

A0+1, A0+2, and A0+3