IS61NLP204818A-166TQI datasheet(3/22 Pages) ISSI

Part #	IS61NLP204818A-166TQI

Description	1Mb x 36 and 2Mb x 18 STATE BUS SRAM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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3 / 22 page

Integrated Silicon Solution, Inc. — www.issi.com

3

Rev. A

09/13/07

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

PIN CONFIGURATION — 1M X 36, 165-Ball PBGA (TOP VIEW)

12

34

56

7

8

9

10

11

ANC

A

CE

BWc

BWb

CE2

CKE

ADV

A

NC

B

NC

A

CE2

BWd

BWa

CLK

WE

OE

AA

NC

C

DQPc

NC

VDDQ

VSS

VDDQ

NC

DQPb

D

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

E

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

F

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

G

DQc

VDDQ

VDD

VSS

VDD

VDDQ

DQb

HNC

NC

VDD

VSS

VDD

NC

ZZ

J

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

K

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

L

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

M

DQd

VDDQ

VDD

VSS

VDD

VDDQ

DQa

NDQPd

NC

VDDQ

VSS

NC

VSS

VDDQ

NC

DQPa

P

NC

A

ANC

A1*

NC

A

ANC

R

MODE

A

NC

A0*

NC

A

Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

(Under Evaluation)

PIN DESCRIPTIONS

Symbol

Pin Name

A

Address Inputs

A0, A1

Synchronous Burst Address Inputs

ADV

Synchronous Burst Address Advance/

Load

WE

Synchronous Read/Write Control

Input

CLK

Synchronous Clock

CKE

Clock Enable

CE, CE2, CE2 Synchronous Chip Enable

BWx (x=a-d)

Synchronous Byte Write Inputs

OE

Output Enable

ZZ

Power Sleep Mode

MODE

Burst Sequence Selection

VDD

3.3V/2.5V Power Supply

NC

No Connect

DQx

Data Inputs/Outputs

DQPx

Parity Data I/O

VDDQ

Isolated output Power Supply

3.3V/2.5V

VSS

Ground

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