Integrated Silicon Solution, Inc.

1

Rev. B

04/17/08

IS61LF102436A IS61VF102436A

IS61LF204818A IS61VF204818A

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• Internalself-timedwritecycle

• IndividualByteWriteControlandGlobalWrite

• Clockcontrolled,registeredaddress,dataand

control

• BurstsequencecontrolusingMODEinput

• Three chip enable option for simple depth expan-

sion and address pipelining

• Commondatainputsanddataoutputs

• AutoPower-downduringdeselect

• Singlecycledeselect

• SnoozeMODEforreduced-powerstandby

• PowerSupply

• JEDEC100-PinTQFPand165-pinPBGApack-

ages.

• Lead-freeavailable

APRIL 2008

1M x 36, 2M x 18

36Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

DESCRIPTION

The

are high-speed, low-power synchronous static RAMs de-

signed to provide burstable, high-performance memory for

communication and networking applications.The IS61LF/

VF102436Aisorganizedas1,048,476wordsby36bits.

The IS61LF/VF204818Aisorganizedas2M-wordsby18

bits. Fabricated with

the device integrates a 2-bit burst counter, high-speed

SRAMcore,andhigh-drivecapabilityoutputsintoasingle

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

Writecyclesareinternallyself-timedandareinitiatedbythe

risingedgeoftheclockinput.Writecyclescanbeoneto

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Bytewriteoperationisperformedbyusingbytewriteen-

able (BWE) input combined with one or more individual

byte write signals (BWx). Inaddition,GlobalWrite(GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

BurstscanbeinitiatedwitheitherADSP (Address Status

Processor)orADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the ADV (burst address

advance) input pin.

Themodepinisusedtoselecttheburstsequenceorder,

LinearburstisachievedwhenthispinistiedLOW.Inter-

leaveburstisachievedwhenthispinistiedHIGHorleft

floating.

FAST ACCESS TIME

Symbol

Parameter

-6.5

-7.5

Units

ClockAccessTime

6.5

7.5

ns

CycleTime

7.5

8.5

ns

Frequency

133

117

MHz