Integrated Silicon Solution, Inc.

1

Rev. B

03/27/08

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

IS61VPS102436A IS61LPS102436A

IS61VPS204818A IS61LPS204818A

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• Power Supply

• JEDEC 100-Pin TQFP and 165-ball PBGA

packages

• Lead-free available

DESCRIPTION

The

204818A are high-speed, low-power synchronous static

RAMsdesignedtoprovideburstable,high-performancememory

for communication and networking applications. The

IS61LPS/VPS102436A is organized as 1,048,476 words

by 36 bits. The IS61LPS/VPS204818A is organized as

2M-word by 18 bits. Fabricated with

CMOS technology, the device integrates a 2-bit burst

counter, high-speed SRAM core, and high-drive capability

outputs into a single monolithic circuit. All synchronous

inputs pass through registers controlled by a positive-

edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (

BWE) input combined with one or more

individual byte write signals (

BWx). In addition, Global

Write (

GW) is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either

ADSP (Address Status

Processor) or

ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

1Mb x 36, 2Mb x 18

36Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

MARCH 2008

FAST ACCESS TIME

Symbol

Parameter

200

166

Units

Clock Access Time

3.1

3.5

ns

Cycle Time

5

6

ns

Frequency

200

166

MHz