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IS61DDPB24M18-400M3L Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
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IS61DDPB24M18-400M3L Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 24 page 8 Integrated Silicon Solution, Inc. Rev. 00A 03/31/08 72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs Timing Reference Diagram for Truth Table Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.) Mode Clock Controls Data-Out/Data-In KLD R/W QA / DB QA+1 / DB+1 Stop Clock Stop X X Previous state Previous state No Operation (NOP) L H H H High-Z High-Z Read A L H L X D out at K (t + 2.5) D out at K (t + 3) Write B L HX L DB (tW + 1) DB (tW + 1.5) Notes: 1. The internal burst counter is always fixed as two-bit. 2. X = don’t care; H = logic “1”; L = logic “0”. 3. A read operation is started when control signal R/W is active high. 4. A write operation is started when control signal R/W is active low. 5. Before entering into the stop clock, all pending read and write commands must be completed. 6. For timing definitions, refer to the AC Characteristics on page 15. Signals must have AC specifications at timings indicated in parenthesis with respect to switching clocks K and K. tt+1 t+2 NOP A QA +1 K Clock K Clock LD R / W BW 0,1,2,3 Address Data-In/ CQ Clock CQ Clock Cycle tw tw+1 DB NOP Read A B W Write B rite B Data-Out (DQ) t+3 t+2.5 QA |
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