PRELIMINARY
CY2XF33
High Performance LVDS Oscillator with
Frequency Margining - Pin Control
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-53148 Rev. *B
Revised September 18, 2009
Features
■ Low Jitter Crystal Oscillator (XO)
■ Less than 1 ps Typical RMS Phase Jitter
■ Differential LVDS Output
■ Output Frequency from 50 MHz to 690 MHz
■ Two Frequency Margining Control Pins (FS0, FS1)
■ Factory Configured or Field Programmable
■ Integrated Phase-Locked Loop (PLL)
■ Supply Voltage: 3.3V or 2.5V
■ Pb-Free Package: 5.0 x 3.2 mm LCC
■ Commercial and Industrial Temperature Ranges
Functional Description
The CY2XF33 is a high performance and high frequency Crystal
Oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed through two select pins, allowing
easy frequency margin testing in applications.
The CY2XF33 is available as a factory configured device or as
a field programmable device.
Pinouts
Figure 1. Pin Diagram - 6 Pin Ceramic LCC
Logic Block Diagram
OUTPUT
DIVIDER
1
FS0
CRYSTAL
OSCILLATOR
LOW -NOISE
PLL
4
CLK
5
CLK#
2
FS1
FREQUENCY
SELECT DECODE
1
3
FS0
VSS
VDD
CLK
6
4
2
5CLK#
FS1
Table 1. Pin Definitions - 6 Pin Ceramic LCC
Pin
Name
I/O Type
Description
1, 2
FS0, FS1
CMOS Input
Frequency Select
4, 5
CLK, CLK#
LVDS Output
Differential Output Clock
6
VDD
Power
Supply Voltage: 2.5V or 3.3V
3
VSS
Power
Ground
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