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PRELIMINARY
CY2XF23
Document Number: 001-53145 Rev. *B
Page 8 of 11
Switching Waveforms
Figure 8. Output Voltage Swing
Figure 9. Output Offset Voltage
Figure 10. Duty Cycle Timing
I2C Bus Timing Specifications[5]
Parameter
Description
Min
Max
Unit
fSCLK
SCLK frequency
–
100
kHz
tHD:STA
Start mode time from SDA LOW to SCLK LOW
4
–
μs
tLOW
SCLK LOW period
4.7
–
μs
tHIGH
SCLK HIGH period
4–
μs
tSU:DAT
Input data setup (SDA transition to SCLK rising edge)
1000
–
ns
tHD:DAT
Input data hold (SCLK falling edge to SDA transition)
0
–
ns
tHD:DO
Output data hold (SCLK falling edge to SDA transition)
200
–
ns
tSR
Rise time of SCLK and SDA
–
300
ns
tSF
Fall time of SCLK and SDA
–
300
ns
tSU:STO
Stop mode time from SCLK HIGH to SDA HIGH
4
–
μs
tBUF
Stop mode to Start mode
4.7
–
μs
CLK
CLK#
V
OD2
V
OD1
ΔV
OD = VOD1 - VOD2
CLK
50
Ω
CLK#
50
Ω
V
OS
CLK
T
PW
T
PERIOD
T
DC =
T
PW
T
PERIOD
CLK#
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