IS42S86400B

IS42S16320B, IS45S16320B

Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. C

08/27/09

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-

out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain

the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• Clockfrequency:166,143,133MHz

• Fullysynchronous;allsignalsreferencedtoa

positive clock edge

• Internalbankforhidingrowaccess/precharge

• Powersupply

IS42/45S16320B 3.3V 3.3V

IS42S86400B

3.3V 3.3V

• LVTTLinterface

• Programmableburstlength

–(1,2,4,8,fullpage)

• Programmableburstsequence:

Sequential/Interleave

• AutoRefresh(CBR)

• SelfRefresh

• 8Krefreshcyclesevery64ms

• Randomcolumnaddresseveryclockcycle

• ProgrammableCASlatency(2,3clocks)

• Burstread/writeandburstread/singlewrite

operations capability

• Burstterminationbyburststopandprecharge

command

• Availablein54-pinTSOP-IIand54-ballW-BGA

(x16only)

• OperatingTemperatureRange:

OVERVIEW

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

The512MbSDRAMisorganizedasfollows.

64M x 8, 32M x 16

512Mb SYNCHRONOUS DRAM

SEPTEMBER 2009

KEY TIMING PARAMETERS

Parameter

-6

-7

-75E Unit

ClkCycleTime

CAS

Latency=3

6

7

–

ns

CAS

Latency=2

10

10

7.5

ns

ClkFrequency

CAS

Latency=3

166

143

–

Mhz

CAS

Latency=2

100

100

133

Mhz

AccessTimefromClock

CAS

Latency=3

5.4

5.4

–

ns

CAS

Latency=2

6

6

5.5

ns

IS42S86400B

IS42/45S16320B

16Mx8x4Banks

8Mx16x4Banks

54-pinTSOPII

54-pinTSOPII

54-ballW-BGA