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IS42S16400F-6TL Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc

Part # IS42S16400F-6TL
Description  1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS42S16400F-6TL Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
11/09/09
IS42S16400F
IS45S16400F
3. Current state definitions:
Idle:Thebankhasbeenprecharged,andtrp has been met.
RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister
accesses are in progress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated.
4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.COMMANDINHIBITorNOPcommands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mandstotheotherbankaredeterminedbyitscurrentstateandCURRENTSTATEBANKntruthtables.
Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentrpismet.Oncetrp is met, the bank
will be in the idle state.
RowActivating:StartswithregistrationofanACTIVEcommandandendswhentrcdismet.Oncetrcd is met, the bank will
be in the row active state.
Readw/Auto
PrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state.
Writew/Auto
PrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state.
5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;COMMANDINHIBITorNOPcommandsmustbe
applied on each positive clock edge during these states.
Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentrcismet.Oncetrc is met, the
SDRAMwillbeintheallbanksidlestate.
Accessing Mode
Register:StartswithregistrationofaLOADMODEREGISTERcommandandendswhentmrdhasbeenmet.Once
tmrdismet,theSDRAMwillbeintheallbanksidlestate.
PrechargingAll:StartswithregistrationofaPRECHARGEALLcommandandendswhentrpismet.Oncetrp is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7.Notbank-specific;requiresthatallbanksareidle.
8.Mayormaynotbebank-specific;ifallbanksaretobeprecharged,allmustbeinavalidstateforprecharging.
9.Notbank-specific;BURSTTERMINATEaffectsthemostrecentREADorWRITEburst,regardlessofbank.
10.READsorWRITEslistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabledand
READsorWRITEswithautoprechargedisabled.
11.DoesnotaffectthestateofthebankandactsasaNOPtothatbank.


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