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MMA8110EG Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MMA8110EG Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 47 page MMA81XXEG Sensors 6 Freescale Semiconductor 1.3.6 CFIL The output of the sensor interface circuitry can be monitored at the CFIL pin. An internal buffer is provided to provide isolation between external signals and the input to the A/D converter. If CFIL monitoring is desired, a low-pass filter and a buffer with high input impedance located as close to this pin as possible are required. The circuit configuration shown in Figure 1-5 is recommended. Figure 1-4. CFIL Filter and Buffer Configuration This pin may be configured as an input to the A/D converter when the MMA81XXEG/MMA82XXEG device is in test mode. Refer to Appendix A for further details regarding test mode operation. 1.3.7 Trim/Test Pins (VPP/TEST, CLK, DOUT) These pins are used for programming the device during manufacturing. These pins have internal pull-up or pull-down devices to drive the input when left unconnected. The following termination is recommended for these pins in the end application: CLK may be connected to ground, however this is not advised if the GLDE bit in DEVCFG2 is set, as a short between the adjacent VGND/DIN pin and ground prevents ground loss detection. 1.3.8 GND Detect Pin (VGND/DIN) VGND/DIN may be used to detect an open condition between the satellite module and chassis. The ground loss detector circuit supplies a constant current through VGND/DIN and measures resulting voltage. This determines the resistance between VGND/ DIN and the system’s virtual ground. A fault condition is signalled if the resistance exceeds specified limits. This pin has no internal pull-down device and must be connected as shown in Figure 1-5. Ground loss detection circuitry is enabled when the GLDE bit is programmed to a logic ‘1’ state in DEVCFG2. Ground loss detection is not available when the master operates in differential mode. VGND/DIN must be directly connected to BUSRTN if the DSI bus is configured for differential operation. VGND/DIN connection options are illustrated in Figure 1-5. When ground loss detection is enabled, a constant current is sourced and the voltage at VGND is continuously monitored. An open connection between VSS and chassis ground will cause the voltage to rise. If the voltage indicates that the connection between chassis ground and VSS has opened, a 14-bit counter is enabled. This counter will reverse if the voltage falls below the detection threshold. Should the counter overflow, a ground loss condition is indicated. The counter acts as a digital low-pass filter, to provide immunity from spurious signals. This pin functions as the SPI data input when the device is in test mode. Table 1-1 PIN Termination VPP/TEST Connect to ground CLK Leave unconnected DOUT Leave unconnected 680 pF 50 k Ω 5 MMA81XXEG/MMA82XXEG CFIL RIN ≥ 1 MΩ |
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