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LPC2460FBD208 Datasheet(PDF) 2 Page - NXP Semiconductors |
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LPC2460FBD208 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 78 page  LPC2420_60_4 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 04 — 15 October 2009 2 of 78 NXP Semiconductors LPC2420/2460 Flashless 16-bit/32-bit microcontroller I EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM. I Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts. I General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP, I2S, and SD/MMC interface as well as for memory-to-memory transfers. I Serial Interfaces: N Ethernet MAC with MII/RMII interface and associated DMA controller (LPC2460 only). These functions reside on an independent AHB. N USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller. N Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. N CAN controller with two channels (LPC2460 only). N SPI controller. N Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. N Three I2C-bus interfaces (one with open-drain and two with standard port pins). N I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. I Other peripherals: N SD/MMC memory card interface. N 160 General purpose I/O pins with configurable pull-up/down resistors. N 10-bit ADC with input multiplexing among 8 pins. N 10-bit DAC. N Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input. N Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs. N RTC with separate power domain. Clock source can be the RTC oscillator or the APB clock. N 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off. N WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. I Standard ARM test/debug interface for compatibility with existing tools. I Emulation trace module supports real-time trace. I Single 3.3 V power supply (3.0 V to 3.6 V). I Four reduced power modes: idle, sleep, power-down, and deep power-down. I Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources. I Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, port 0/2 pin interrupt, Ethernet wake-up interrupt (LPC2460 only), CAN bus activity (LPC2460 only)). I Two independent power domains allow fine tuning of power consumption based on needed features. |
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Similar Description - LPC2460FBD208 |
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